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ds04-21379-1e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 3.0 ghz prescaler MB15E06SR n description the fujitsu MB15E06SR is a serial input phase locked loop (pll) frequency synthesizer with a 3.0 ghz prescaler. the 3.0 ghz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. the supply voltage range is between 2.7 v and 4.0 v. a refined charge pump supplies well-balanced output currents of 4.0 ma. the phase noise of MB15E06SR was drastically improved comparing with the former single pll, mb15e06. the data format of serial data and the pin assignments except for f p and f r pins are same as the former one, so it is easy to replace the former one. MB15E06SR is ideally suited for the high frequency wireless system such as etc (electronic toll collection system). n features ? high frequency operation: 3.0 ghz max ? low power supply voltage: v cc = 2.7 v to 4.0 v ? ultra low power supply current: i cc = 8.0 ma typ (v cc = vp = 3.0 v, ta = +25 c, in locking state) ? direct power saving function:power supply current in power saving mode typ 0.1 m a (v cc = vp = 3.0 v, ta = +25 c) (continued) n packages 16-pin plastic tssop (fpt-16p-m07) 16-pad plastic bcc (lcc-16p-m06)
MB15E06SR 2 (continued) ? dual modulus prescaler: 64/65 or 128/129 ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? software selectable charge pump current ? on-chip phase control for phase comparator ? built-in digital locking detector circuit to detect pll locking and unlocking. ? operating temperature: ta = C40 c to +85 c n pin assignments osc in osc out v p v cc d o gnd xfin fin n.c. n.c. ld/fout n.c. ps le data clock 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 osc out v p v cc d o gnd xfin n.c. ld/fout n.c. ps le data osc in n.c. fin clock 1 2 3 4 5 678 9 10 11 12 13 14 15 16 (fpt-16p-m07) (lcc-16p-m06) 16-pin tssop 16-pad bcc top view top view
MB15E06SR 3 n pin descriptions pin no. pin name i/o descriptions tssop bcc 116osc in i programmable reference divider input. connection to a tcxo. 21osc out o oscillator output. 32v p C power supply voltage input for the charge pump. 43v cc C power supply voltage input. 54d o o charge pump output. phase of the charge pump can be selected via programming of the fc bit. 6 5 gnd C ground. 7 6 xfin i prescaler complementary input, which should be grounded via a capacitor. 87fini prescaler input. connection to an external vco should be done via ac coupling. 98clocki clock input for the 19-bit shift register. data is shifted into the shift register on the rising edge of the clock. (open is prohibited.) 10 9 data i serial data input using binary code. the last bit of the data is a control bit. (open is prohibited.) 11 10 le i load enable signal input. (open is prohibited.) when le is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. 12 11 ps i power saving mode control. this pin must be set at l at power-on. (open is prohibited.) ps = h; normal mode ps = l; power saving mode 13 12 n.c. C no connection. 14 13 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected via programming of the lds bit. lds = h; outputs fout (fr/fp monitoring output) lds = l; outputs ld (h at locking, l at unlocking.) 15 14 n.c. C no connection. 16 15 n.c. C no connection.
MB15E06SR 4 n block diagram fin ps osc in d o clock le ld / fout xfin gnd sw v p c n t fp (16) (11) (10) (6) (9) (8) (7) (5) (13) (2) (4) 14 3 5 6 8 9 7 11 12 1 (3) 4 data v cc 7-bit latch 11-bit latch sw fc lds reference oscillator circuit binary 14-bit reference couter 14-bit latch 3-bit latch phase comparator lock detector 19-bit shift register intermittent mode control (power save) 1-bit control latch binary 7-bit swallow counter binary 11-bit programmable counter charge pump prescaler 64/65 128/129 10 ld/fr/fp selector osc out (1) 2 : tssop ( ) : bcc
MB15E06SR 5 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol condition rating unit remark min max power supply voltage v cc C C0.5 5.0 v v p Cv cc 6.0 v input voltage v i C C0.5 v cc +0.5 v output voltage v o except do gnd v cc v v o do gnd v p v storage temperature tstg C C55 +125 c parameter symbol value unit remark min typ max power supply voltage v cc 2.7 3.0 4.0 v v p v cc C5.5v input voltage v i gnd C v cc v operating temperature ta C40 C +85 c
MB15E06SR 6 n electrical characteristics (v cc = 2.7 v to 4.0 v, ta = C40 c to +85 c) *1: conditions; fosc = 13 mhz, vosc = 1.2 v pp , ta = +25 c, in locking state. *2: v cc = v p = 3.0 v, fosc = 13 mhz, vosc = 1.2 v pp , ta = +25 c, in power saving mode *3: ac coupling. 1000 pf capacitor is connected under the condition of min. operating frequency. *4: the symbol C (minus) means direction of current flow. *5: v cc = v p = 3.0 v, ta = +25 c (||i 3 | C |i 4 ||) / [(|i 3 | + |i 4 |) /2] 100(%) *6: v cc = v p = 3.0 v, ta = +25 c [(||i 2 | C |i 1 ||) /2] / [(|i 1 | + |i 2 |) /2] 100(%) (applied to each i dol , i doh ) (continued) parameter symbol condition value unit min typ max power supply current* 1 i cc fin = 3000 mhz, v cc = v p = 3.0 v 6.0 8.0 11.5 ma power saving current i ps ps = l C 0.1 *2 20 m a operating frequency fin f in C 700 C 3000 mhz osc in fosc C 3 C 40 mhz input sensitivity fin *3 pfin 50 w system (refer to the measurement circuit.) C10 C +2 dbm osc in *3 v osc C0.5Cv cc vp-p h level input voltage data, clock, le, ps v ih Cv cc 0.7 C C v l level input voltage v il CCCv cc 0.3 h level input current data, clock, le, ps i ih *4 C C1.0 C +1.0 m a l level input current i il *4 C C1.0 C +1.0 h level input current osc in i ih C0C+100 m a l level input current i il *4 C C100 C 0 h level output voltage ld/fout v oh v cc = v p = 3.0 v, i oh = C1 ma v cc C 0.4 C C v l level output voltage v ol v cc = v p = 3.0 v, i ol = 1 ma C C 0.4 h level output voltage do v doh v cc = v p = 3.0 v, i doh = C0.5 ma v p C 0.4 C C v l level output voltage v dol v cc = v p = 3.0 v, i dol = 0.5 ma C C 0.4 high impedance cutoff current do i off v cc = v p = 3.0 v, v off = 0.5 v to v p C 0.5 v CC2.5na h level output current ld/fout i oh v cc = v p = 3.0 v C C C1.0 ma l level output current i ol v cc = v p = 3.0 v 1.0 C C h level output current do i doh *4 v cc = v p = 3.0 v, v do = v p /2, ta = +25 c C5.2 C4.0 C2.8 ma l level output current i dol 2.8 4.0 5.2 charge pump current rate i dol / i doh i domt *5 v do = v p /2 C 5 C % vs v do i dovd *6 0.5 v v do v p C 0.7 v C 10 C % vs ta i dota *7 C 40 c ta +85 c, v do = v p /2 C 5 C %
MB15E06SR 7 (continued) *7: v cc = v p = 3.0 v, v do = v p /2 (||i do(+85 c) | C |i do(C40 c) | |/2) / (||i do(+85 c) | + |i do(C40 c) || /2) 100(%) (applied to each i dol , i doh ) i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 charge pump output voltage (v) v p /2 v p v p - 0.7
MB15E06SR 8 n functional description 1. pulse swallow function the divide ratio can be calculated using the following equation: f vco = [(p n) + a] f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) p : preset divide ratio of modulus prescaler (64 or 128) 2. serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the le signal pin is taken high, stored data is latched according to the control bit data as follows: table 1. control bit (1) shift register configuration control bit (cnt) destination of serial data h for the programmable reference divider l for the programmable divider 1 23456789101112131415161718 cntr1r2r3r4r5r6r7r8r9r10r11r12r13r14swfc lds programmable reference counter msb data flow cnt : control bit [table 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (3 to 16,383) [table 2] sw : divide ratio setting bit for the prescaler (64/65 or 128/129) [table 5] fc : phase control bit for the phase comparator [table 7] lds : ld/f out signal select bit [table 6] note: start data input with msb first. lsb
MB15E06SR 9 table 2. binary 14-bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. table 3. binary 11-bit programmable counter data setting note : divide ratio less than 3 is prohibited. divide ratio(r) r14r13r12r11r10r9r8r7r6r5r4r3r2r1 3 0 0 0 0 0 000000011 4 0 0 0 0 0 000000100 16383 1 1 1 1 1 111111111 divide ratio(n) n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 00000000011 4 00000000100 2047 1 1 111111111 1 2345678910111213141516171819 cnt a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 programmable counter lsb msb data flow cnt : control bit [table 1] n1 to n11: divide ratio setting bits for the programmable counter (3 to 2,047) [table 3] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table 4] note: data input with msb first.
MB15E06SR 10 table 4. binary 7-bit swallow counter data setting table 5. prescaler data setting table 6. ld/fout output select data setting (2) relation between the fc input and phase characteristics the fc bit changes the phase characteristics of the phase comparator. the internal charge pump output level (d o ) is reversed according to the fc bit. also, the monitor pin (fout) output is controlled by the fc bit. the relationship between the fc bit and d o is shown below. table 7. fc bit data setting (lds = 1) z : high impedance divide ratio (a)a7a6a5a4a3a2a1 0 0000000 1 0000001 127 1111111 sw prescaler divide ratio 1 64/65 0 128/129 lds ld/ fout output signal 1 fout signal 0 ld signal fc = 1 fc = 0 d o ld/fout d o ld/fout fr > f p h fout = fr l fout = fp fr < f p lh fr = f p zz
MB15E06SR 11 when designing a synthesizer, the fc pin setting depends on the vco and lpf characteristics. (1) (2) ? when the lpf and vco characteristics are similar to (1), set fc bit high. ? when the vco characteristics are similar to (2), set fc bit low. vco output frequency lpf output voltage pll lpf vco note : give attention to the polarity for using active type lpf.
MB15E06SR 12 3. power saving mode (intermittent mode control circuit) table 10. ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the signal pll, the lock detector, ld, remains high, indicating a locked condition. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes : when power (v cc ) is first applied, the device must be in standby mode, ps = low. the serial data input after the power supply becomes stable and the the power saving mode is released after completed the data input. . ps pin status h normal mode l power saving mode on off v cc clock data le ps (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps = l (power saving mode) at power on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps: l ? h) 100 ns later after setting serial data.
MB15E06SR 13 n serial data input timing 1st data 2nd data control bit invalid data data clock le msb lsb t 1 t 2 t 3 t 6 t 5 t 4 t 0 ~ ~ ~ ~ note: le should be l when the data is transferred into the shift register. parameter min typ max unit t 1 20 C C ns t 2 20 C C ns t 3 30 C C ns t 4 30 C C ns parameter min typ max unit t 5 100 C C ns t 6 20 C C ns t 7 100 C C ns on the rising edge of the clock, one bit of data is transferred into the shift register.
MB15E06SR 14 n phase comparator output waveform fr fp ld d o d o t wu t wl notes: phase error detection range: C2 p to +2 p pulses on do signal during locked state are output to prevent dead zone. ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency. t wu > 2/fosc (s) (e. g. t wu > 153.8 ns, fosc = 13 mhz) t wu < 4/fosc (s) (e. g. t wl < 307.7 ns, fosc = 13 mhz) ld becomes high during the power saving mode (ps = l). [fc = 1] [fc = 0]
MB15E06SR 15 n measurment circuit (for measuring input sensitivity fin/osc in ) s.g. 50 w 1000 pf s.g. 50 w 1000 pf 0.1 m f 0.1 m f 86 43 1 9101112 14 75 2 13 15 16 1000 pf v cc fin xfin gnd d o v cc v p osc in clock data le ps n.c. ld / fout n.c. n.c. controller (setting divide ratio) oscilloscope osc out note: tssop-16
MB15E06SR 16 n typical characteristics 1. fin input sensitivity 2. osc in input sensitivity 10 0 - 15 - 20 - 30 - 35 0 500 1000 1500 2000 2500 3000 3500 4500 ta = + 25 c 4000 catalog guaranteed range v cc = 2.7 v v cc = 3.0 v v cc = 4.0 v spec - 25 5 - 5 - 10 input sensitivity - input frequency input frequency f in (mhz) input sensitivity pfin (dbm) 10.0 0.0 - 10.0 - 20.0 - 30.0 - 40.0 - 50.0 0 20 40 60 80 100 120 180 v cc = 2.7 v v cc = 3.0 v v cc = 3.75 v ta = + 25 c 140 160 spec input sensitivity - input frequency input frequency f osc (mhz) input sensitivity v osc (dbm) catalog guaranteed range
MB15E06SR 17 3. do output current 4. fin input impedance 10.00 - 10.00 37 ta = +25?c, v cc = v p = 3.0 v 012 456 0.00 2.00 ma/div ? 4.0 ma v do - i do charge pump output current i do (ma) charge pump output voltage v do (v) 27.688 w - 105.31 w 700 mhz 18.004 w - 64.969 w 1 ghz 18.395 w 1.0674 w 2 ghz 1 : 2 : 3 : 3 2 start 700.000 000 mhz stop 3 000.000 000 mhz 4 4: 75.418 w 63.625 w 3.3754 nh 3 000.000 000 mhz 1
MB15E06SR 18 5. osc in input impedance 5.771 k w - 15.199 k w 3 mhz 133.63 w - 2.5508 k w 20 mhz 56.25 w - 1.3956 k w 40 mhz 1 : 2 : 3 : 3 2 start 3.000 000 mhz stop 40.000 000 mhz 4 1 4: 56.25 w - 1.3356 k w 2.979 pf 40.000 000 mhz
MB15E06SR 19 n reference information (continued) atten 10 db rl - 10.0 dbm vavg 16 10 db / d mkr - 77.67 db 100.0 khz center 1.6190000 ghz rbw 3.0 khz vbw 3.0 khz span 300.0 khz swp 84.0 ms d mkr 100.0 khz - 77.67 db s.g. spectrum analyzer osc in fin do lpf vco test circuit f vco = 1619 mhz k v = 44 mhz/v fr = 100 khz f osc = 10 mhz (1.2 v pp ) v cc =v p = 3.0 v v vco = 3.0 v ta = +25 c cp : 4 ma 27 k w 3.3 k w 15000 pf 120 pf 2200 pf lpf atten 10 db rl - 10.0 dbm vavg 16 10 db / d mkr - 78.84 db/hz 1.000 khz center 1.619000000 ghz rbw 30 hz vbw 30 hz span 5.000 khz swp 969 ms d mkr 1.000 khz - 78.84 db/hz ? pll reference leakage ? pll phase noise
MB15E06SR 20 (continued) 1.672003384 ghz 1.671999384 ghz 1.671995384 ghz d mkr x : - 289.99777 m s y : - 23.8776 mhz 5.000 ms 0.00 s 1597.2 mhz 1672 mhz 1 khz lch hch 1.06 ms 2.500 ms d mkr x : - 300.00071 m s y : - 23.8754 mhz 1672 mhz 1597.2 mhz 1khz hch lch 0.9 ms 1.597203471 ghz 1.597199471 ghz 1.597195471 ghz 5.000 ms 0.00 s 2.500 ms ? pll lock up time ? pll lock up time
MB15E06SR 21 n application example n usage precautions to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting device into or removing device from a socket. -protect leads with a conductive sheet when transporting a board-mounted device. 0.1 m f 1000 pf output lpf vco 16 15 14 13 12 11 10 9 123 4 56 78 0.1 m f 1000 pf tcxo 1000 pf lock det. n.c. n.c. ld/fout n.c. clock MB15E06SR from a controller ps le data osc in v p v cc d o gnd xfin fin osc out v p : 5.5 v max note: tssop-16
MB15E06SR 22 n ordering information part number package remarks MB15E06SRpft 16-pin, plastic tssop (fpt-16p-m07) MB15E06SRpv1 16-pad, plastic bcc (lcc-16p-m06)
MB15E06SR 23 n package dimensions (continued) 16-pin, plastic tssop (fpt-16p-m07) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited f16020s-c-3-3 5.000.10(.197.004) 4.400.10 6.400.20 (.252.008) (.173.004) 0.10(.004) 0.65(.026) 0.240.08 (.009.003) 1 8 16 9 "a" 0.170.05 (.007.002) m 0.13(.005) details of "a" part 0~8 ? (.024.006) 0.600.15 (0.50(.020)) 0.25(.010) (.041.002) 1.050.05 (mounting height) 0.07 +0.03 C0.07 +.001 C.003 .003 (stand off) lead no. index * 1 * 2
MB15E06SR 24 (continued) 16-pad plastic bcc (lcc-16p-m06) dimensions in mm (inches) . note : the values in parentheses are reference values. c 1999 fujitsu limited c16017s-1c-1 0.325?.10 (.013?004) 3.40(.134)typ "a" 0.40?.10 (.016?004) 2.45(.096) 0.80(.031) ref typ 4.55?.10 (.179?004) 0.80(.031)max mounting height 0.075?.025 (.003?001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.40?.10 (.016?004) 0.75?.10 (.030?004) details of "a" part 1.725(.068) ref 1.15(.045) ref "b" details of "b" part (.024?004) 0.60?.10 (.024?004) 0.60?.10 0.65(.026) typ index area (.134?004) 3.40?.10
MB15E06SR fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0401 ? fujitsu limited printed in japan

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